Vertical replacement-gate junction field-effect transistor

ABSTRACT

An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

This patent application is a continuation of U.S. patent applicationSer. No. 10/723,547 filed on Nov. 26, 2003, which is a divisional ofU.S. patent application Ser. No. 09/950,384 filed on Sep. 10, 2001, nowU.S. Pat. No. 6,690,040.

FIELD OF THE INVENTION

The present invention is directed to semiconductor devices incorporatingjunctions of varying conductivity types and methods of making suchdevices. More specifically, the present invention is directed tovertical replacement-gate (VRG) junction field-effect transistor devicesand methods for fabricating integrated circuits incorporating suchdevices.

BACKGROUND OF THE INVENTION

Enhancing semiconductor device performance and increasing device density(the number of devices per unit area), continue to be importantobjectives of the semiconductor industry. Device density is increased bymaking individual devices smaller and packing devices more compactly.But, as the device dimensions (also referred to as the feature size ordesign rules) decrease, the methods for forming devices and theirconstituent elements must be adapted. For instance, production devicesizes are currently in the range of 0.25 microns to 0.12 microns, withan inexorable trend toward smaller dimensions. However, as the devicedimensions shrink, certain manufacturing limitations arise, especiallywith respect to the lithographic processes. In fact, currentlithographic processes are nearing the point where they are unable toaccurately manufacture devices at the required minimal sizes demanded bytoday's device users.

Currently most metal-oxide-semiconductor field effect transistors(MOSFETs) are formed in a lateral configuration, with the currentflowing parallel to the major plane of the substrate or body surface. Asthe size of these MOSFET devices decreases to achieve increased devicedensity, the fabrication process becomes increasingly difficult. Inparticular, the lithographic process for creating the gate channel isproblematic, as the wavelength of the radiation used to delineate animage in the lithographic pattern approaches the device dimensions.Therefore, for lateral MOSFETs, the gate length is approaching the pointwhere it cannot be precisely controlled through the lithographictechniques.

Like MOSFETs, junction field-effect transistors (JFETs) have been formedusing lithographically defined channel lengths. As the channel lengthdecreases to increase device density, the channel length may not becontrollable using conventional photolithographic techniques. Instead,expensive x-ray and electron beam lithographic equipment may be requiredfor the formation of both MOSFETs and JFETs with state-of-the-artchannel lengths.

Generally, integrated circuits comprise a plurality of active devices,including MOSFETs, JFETs and bipolarjunction transistors, as well aspassive components such as resistors and capacitors. Commonly owned U.S.Pat. Nos. 6,027,975 and 6,197,441, which are hereby incorporated byreference, teach certain techniques for the fabrication of verticalreplacement gate (VRG) MOSFETs. It is therefore advantageous tofabricate JFETs using similar and compatible processing steps as thoseemployed for the fabrication of MOSFETs to reduce integrated circuitfabrication costs.

BRIEF SUMMARY OF THE INVENTION

To provide further advances in the fabrication of JFETs having gatelengths precisely controlled through a deposited film thickness, anarchitecture is provided for fabricating vertical replacement gate (VRG)JFET devices.

According to one embodiment of the invention, a semiconductor deviceincludes a first layer of semiconductor material and a first dopedregion formed therein. A second doped region of a different conductivitytype than the first region is formed over the first region. A thirddoped region is formed over the second doped region, with a differentconductivity type than the second doped region.

The first region is a source/drain region of a junction field-effecttransistor, and the second doped region is the channel. The secondsource/drain region is formed over the channel and comprises the thirddoped region.

In an associated method of manufacture, an integrated circuit structureis fabricated by providing a semiconductor layer suitable for deviceformation and having a first surface formed along a first plane. For aJFET device, a first device region is formed in the semiconductor layer,wherein the device region is selected from among a source and a drainregion. A gate region for the JFET is formed above the first deviceregion. In fabricating the vertical JFET, the gate length is preciselycontrolled through the use of a sacrificial layer. Both JFETs andMOSFETs can be fabricated using the same basic fabrication process.

A JFET fabricated according to the teachings of the present inventionprovides a uniform depletion layer (or a uniform pinch-off condition)because the gate completely surrounds the channel and the channel isuniformly doped along a horizontal cross-section. In the prior art, thechannel is oriented horizontally and the carriers flow horizontallythrough it. The channel is formed by diffusion into the semiconductorsubstrate and thus the upper channel region has a higher doping densitythen the lower region. As a result, the depletion layer is not uniformalong any given vertical. Also, creating dual wells in a semiconductorsubstrate according to the present invention allows the fabrication ofclosely matched JFET pairs.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more easily understood and the furtheradvantages and uses thereof more readily apparent, when considered inview of the description of the preferred embodiments and the followingfigures in which:

FIGS. 1A through 1R illustrate, in cross-section, a circuit structureaccording to one embodiment of the invention during sequentialfabrication steps.

In accordance with common practice, the various described features arenot drawn to scale, but are drawn to emphasize specific featuresrelevant to the invention. Reference characters denote like elementsthroughout the figures and text.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

With regard to the fabrication of transistors and integrated circuits,the term “major surface” refers to that surface of the semiconductorlayer in and about which a plurality of transistors are fabricated,e.g., in a planar process. As used herein, the term “vertical” meanssubstantially orthogonal with respect to the major surface. Typically,the major surface is along a <100> plane of a monocrystalline siliconlayer on which the field-effect transistor devices are fabricated. Theterm “vertical transistor” means a transistor with individualsemiconductor components vertically oriented with respect to the majorsurface so that the current flows vertically from source to drain. Byway of example, for a vertical JFET the source, channel and drainregions are formed in relatively vertical alignment with respect to themajor surface.

FIGS. 1A through 1R illustrate cross-sectional views of an integratedcircuit structure 200 during various stages of fabrication to form anexemplary device according to the present invention. From thedescription, it will become apparent how a vertical replacement gatejunction field-effect transistor can be fabricated, either independentlyor in conjunction with the fabrication of a vertical replacement gatemetal-oxide-semiconductor field-effect transistor.

The fabrication process for forming both a VRG MOSFET and JFET isillustrated with reference to FIGS. 1A through 1R. The formation of botha VRG MOSFET and a VRG JFET are illustrated to demonstrate thecompatibility of fabricating both device types in a single fabricationprocess. However, the invention is not limited to embodiments wherein aVRG MOSFET are a VRG JFET are fabricated in a side-by-side orientationor even in the same process. The various semiconductor features andregions described therein are preferably composed of silicon, but itknown to those skilled in the art that other embodiments of theinvention may be based on other semiconductor materials, includingcompound or hereto junction semiconductors alone or in combination.

Referring to FIG. 1A, a heavily doped source region 205 is formed in asilicon substrate 200, preferably a substrate having a <100> crystalorientation along an exposed major surface 203. In this illustration, ofa vertical MOSFET and a vertical JFET, the source region of the deviceis formed in the silicon substrate and the drain region is formed atop asubsequently formed vertical channel, as will be discussed further.Alternatively, the drain region may be formed in the substrate with thesource region formed atop the vertical channel. The former embodiment isthe subject of this description. However, from this description, oneskilled in the art can easily form a device in which the drain region isformed in the silicon substrate and the source region is formedoverlying the subsequently formed vertical channel.

The depth of the heavily doped source region 205, the concentration ofthe dopant therein and the type of dopant (e.g., n-type or p-type) areall matters of design choice. An exemplary source region 205, whereinthe dopant is phosphorous (P), arsenic (As), antimony (Sb) or boron (B)has a dopant concentration in the range of about 1×10¹⁹ atoms/cm³ toabout 5×10²⁰ atoms/cm³. A source region depth of about 200 nm issuitable. Preferably, the source region 205 is formed by a high dose ionimplantation in the range of 1×10⁴ to 1×10¹⁶ atoms/cm² with an energy of1 to 100 KeV.

In FIG. 1B, multiple material layers are formed over the source region205 in the silicon substrate 200. In one embodiment, five layers ofmaterial 210, 211, 215, 216 and 220 are formed over the source region205 in the silicon substrate 200. The insulating layer 210 insulates thesource region 205 from what will eventually be the overlying gate. Thus,the insulating layer 210 is composed of a material and has a thicknessthat is consistent with this insulating objective. Examples of suitablematerials include doped silicon oxide. The use of doped insulating layeris advantageous because in certain embodiments, the insulating layer 210serves as a dopant source, as will be explained further hereinbelow, todope the subsequently formed source/drain extension regions in thevertical device channel. One example of a silicon oxide doping source isPSG (phospho-silicate glass, i.e., a phosphorous-doped silicon oxide) orBSG (boro-silicate glass, i.e., a boron-doped silicon oxide). Oneskilled in the art is aware of suitable expedients for forming a layerof PSG or BSG on a substrate, e.g., plasma-enhanced chemical vapordeposition (PECVD). Suitable thicknesses for the insulating layer 210are in the range of about 25 nm to about 250 nm. The insulating layer210 contains a high concentration of dopant on the order of 1×10²¹/cm³.

An etch stop, as is known to those skilled in the art, is designed toprevent an etch from proceeding to an underlying or overlaying layer orlayers. The etch stop therefore, has a significantly greater etchresistance to a selected etchant than the adjacent layer or layers to beetched. Specifically in this case, for the selected etchant, the etchrate of the etch stop layer (or offset spacer) 211 is much slower thanthe etch rate of the overlying layer, which, as will be discussed below,is a sacrificial layer. According to the present invention, for removalof a sacrificial layer of silicon oxide (e.g., silicon oxide formed fromtetraethylene ortho silicate (TEOS)), an appropriate etch stop materiallimits action of the etchant on the underlying layer.

An etch stop layer 211 is formed over the insulating layer 210. Siliconnitride (Si₃N₄) is a suitable etch stop material. The thickness of theetch stop layer is dependent upon the resistance of the etch stopmaterial to the selected etchant, relative to the material thickness tobe removed through the etch process. In addition to preventing theetchant from acting on the underlying layer, the etch stop layer 211also serves as a diffusion barrier to the dopants used to create thesource/drain extensions, thereby defining the spacing and length of thesource/drain extensions relative to the gate. The etch stop layer 211has a thickness ranging between about 5 nm and about 50 nm.

A sacrificial layer 215 is formed (for example by a TEOS depositionprocess) over the etch stop layer 211. In subsequent processing, thesacrificial layer 215 is removed and the gate of the device formed inthe space vacated by the sacrificial layer 215. Thus, the insulatingmaterial of the sacrificial layer 215 is chosen such that the etchanthas a significantly higher selectivity to remove the sacrificial layer215 relative to the etch stop layer 211. The thickness of thesacrificial layer 215 is selected to correspond to the channel length ofthe final device. Polycrystalline silicon is an example of a suitablesemiconductor material for the sacrificial layer 215.

Preferably, the sacrificial layer 215 is deposited by decomposition of atetraethyl orthosilicate precursor, or TEOS, Si(OC₂H₅)₄. Decompositionof vaporized liquid TEOS to form a silicon oxide film (referred toherein as a TEOS-deposited oxide) typically occurs by chemical vapordeposition (CVD) at 650° C. to 750° C. in an oxygen environment. SuchTEOS depositions are known to provide good uniformity and step coveragewhen needed. Generally, the deposited film is understood to be anon-stoichiometric oxide of silicon, although it is often referred to assilicon dioxide. Inclusion of ozone (O₃), e.g., up to 10 percent of thereacting oxygen, facilitates lower temperature deposition. A typicalreaction, which includes ozone, is performed at 400° C. and 300 Torrwith 4 standard liters per minute (slm) oxygen, the oxygen comprising 6percent ozone, 1.5 slm He and 300 standard cubic centimeters per minute(sccm) TEOS.

An etch stop layer (or offset spacer) 216 is also formed over thesacrificial layer 215. The etch stop layer 216 serves a similar functionas the layer 211 and may, for example, be silicon nitride.

An insulating layer 220 is formed over the etch stop layer 216. Becauseit is advantageous that the insulating layer 220 have the same etch rateas the insulating layer 210 (for a common etchant), it is preferred thatthe insulating layers 210 and 220 be formed of the same material, e.g.PSG pr BSG, which may also serve as a dopant source.

All of the layers 210, 211, 215, 216 and 220 may be deposited usingconventional chemical vapor deposition (CVD) process or other well-knowndeposition techniques. With regard to the aforedescribed sequence oflayers, it should be noted that other embodiments may includesignificant variations, for example, fewer deposited layers. In anycase, the resulting structure will be used to form two vertical channelregions, one for the MOSFET device and the other for the JFET device.

Referring to FIG. 1 C, openings or windows 225 and 227 areanisotropically etched through the insulating layer 210, the etch stoplayer 211, the sacrificial layer 215, the etch stop layer 216 and theinsulating layer 220, downwardly to the source region 205 of the siliconsubstrate 200. The window diameter is determined by the performancecharacteristics and size constraints for the device under fabrication,and the limitations of the lithographic process utilized to form thewindow. The length of the windows 225 and 227 (also referred to as atrench), i.e., the length being orthogonal to both the horizontal andvertical dimensions in the FIG. 1C cross-section, is largely a matter ofdesign choice and are not necessarily identical. For a given horizontaldimension, the current capacity of the doped region to be formed laterin the windows 225 and 227 increases with increasing window length.

The windows 225 and 227 are then subjected to a chemical cleaningprocess, (e.g., RCA or piranha-clean) to clean the silicon at the bottomof the windows 225 and 227. As a result of this cleaning step, smallportions of the insulating layers 210 and 220 forming a boundary withthe windows 225 and 227 are removed. The indentations created areillustrated in FIG. 1D. As shown, the sacrificial layer 215 and the etchstop layers 211 and 216 extend beyond the edge of the insulating layers210 and 220.

Referring to FIG. 1E, the windows 225 and 227 are filled with adevice-quality crystalline semiconductor material (e.g., silicon) 230and 231, respectively. Other examples of crystalline semiconductormaterials that can be utilized include silicon-germanium andsilicon-germanium-carbon. The windows 225 and 227 are formed in anundoped or lightly doped condition. Techniques for forming crystallinesemiconductor material in windows are well known. For example, thecrystalline semiconductor materials 230 and 231 can be grown epitaxiallyin the windows 225 and 227 using the source region 205 as a seed layer.In another embodiment, amorphous or polycrystalline silicon is depositedover the entire substrate 200 and all but the crystalline semiconductormaterial 230 and 231 in the windows 225 and 227 respectively, and topportions 232 and 233 thereof is removed. The amorphous semiconductormaterial is then annealed, e.g., with a laser, to re-crystallize it.

The crystalline semiconductor material 230 formed in the window 225forms the channel of the MOSFET device. The crystalline semiconductormaterial 231 formed in the window 227 forms the channel of the JFETdevice. Therefore the crystalline semiconductor material 230 and 231must be doped to form the channel as well as the source and drainextensions. Dopants of one type (i.e., n-type or p-type) are introducedinto the crystalline semiconductor material 230 and 231 to form sourceand drain extensions, and dopants of the opposite conductivity type areintroduced into the crystalline semiconductor materials 230 and 231 toform the channel. A variety of techniques to dope the crystallinesemiconductor materials 230 and 231 as required are contemplated assuitable. In-situ doping of the crystalline semiconductor materials 230and 231 during formation or implantation of dopants into the crystal andsemiconductor materials 230 and 231 after formation are also suitableprocesses.

In situ dopant introduction, i.e., as a layer of material is formed viachemical vapor deposition, is well known and not described herein. Note,the dopants are introduced into the atmosphere at the appropriate pointin the deposition process to produce the desired concentration as afunction of layer depth. To form the source/drain extensions, dopantsmay be diffused out from the substrate 200 into the bottom of thecrystalline semiconductor materials 230 and 231. Ion implantation isalso a suitable expedient for creating the source/drain extensionregions at the top of the crystalline semiconductor materials 230 and231.

After the crystalline semiconductor materials 230 and 231 are doped andthe dopants distributed therein in the desired manner, the integratedcircuit structure 200 is not subjected to conditions that maysignificantly affect the distribution of the dopant in the crystallinesemiconductor materials 230 and 231. Preferably, but not necessarily,after this step, the integrated circuit structure 200 is not exposed totemperatures that exceed 1100 degrees C. In fact, it is advantageous ifthe integrated circuit structure 200 is not exposed to temperatures inexcess of 1000 degrees C. In certain embodiments, the substrate is notexposed to temperatures that exceed 900 degrees C. for prolonged periodsof time (e.g. in excess of several minutes). However, the integratedcircuit structure 200 can be subjected to rapid thermal annealing attemperatures of about 1000 degrees C. without adversely affecting thedistribution of the dopants. Alternatively, subsequent high temperatureprocessing may be designed to produce the desired dopant distributions.

After the windows 225 and 227 are filled and doped as discussed above,the top portions 231 and 232 are removed, for example, bychemical/mechanical polishing. The results of this process areillustrated in FIG. 1F.

As shown in FIG. 1G, a conformal drain layer 235 is formed over theinsulating layer 220 and the top portions 231 and 232. The drain layer235 provides a self-aligned top contact (the drain contact in thisembodiment). One example of the suitable material for the drain layer235 is doped polycrystalline silicon. The selected dopant is opposite intype to that used to dope the MOSFET and JFET channels. Theconcentration of the dopant is greater than about 1×10²⁰ atoms/cm³.

As further illustrated in FIG. 1G, a conformal layer 236 is depositedover the drain layer 235. The material selected for the layer 236 isselected to have an etch rate that is significantly lower than the etchrate of the sacrificial layer 215. Preferably, the material selected forthe layer 236 is the same as the material of the etch stop layers 211and 216, but preferably is thicker than the layers 211 and 216. Oneexample of a suitable material is silicon nitride. The layer 236 isformed over the drain layer 235 using known techniques.

Using conventional lithographic techniques, the drain layer 235, thelayer 236 and the insulating layer 220 are patterned (using one or moredry etch steps) so that the only remaining portions are those eitheroverlying or adjacent the crystalline semiconductor material 230 or 231.See FIG. 1H.

As illustrated in FIG. 1I, a conformal layer 240 is then deposited. Fora given etch chemistry, the material for the layer 240 is selected tohave an etch rate that is significantly lower than the etch rate of thesacrificial layer 215. One example of a suitable material for the layer240 is silicon nitride. The thickness of the layer 240 is selected sothat the remaining portions of the drain layer 235, the layer 236 andthe insulating layer 220 are protected from contact with subsequentetchants.

The layer 240 is then etched using an anisotropic etch such as dryplasma etch, which also removes a portion of the etch stop layer 216.Therefore, as shown in FIG. 1J, the only portions of the layer 240 thatremain after the anisotropic etch are sidewall portions laterallyadjacent to the insulating layer 220 and the layers 235 and 236. As aresult of this etch process, the sacrificial layer 215 is now exposed.

The device is then subjected to a wet etch (e.g., an aqueoushydrofluoric acid) or an isotropic dry etch (e.g., an anhydroushydrofluoric acid) which removes the exposed remaining portion of thesacrificial layer 215. The result is illustrated in FIG. 1K, where theinsulating layer 210 is still covered by the etch stop layer 211. Theinsulating layer 220 and the drain layer 235 are encapsulated by theremaining portion of the etch stop layer 216 and the layers 236 and 240.Consequently, the remaining portions of the insulating layers 210 and220 and the drain layer 235 remain isolated from contact with subsequentetch expedients.

Referring to FIG. 1L, a sacrificial layer of thermal silicon dioxide 245is grown on the exposed surface of the crystalline semiconductormaterial 230 and 231, to a thickness on the order of less than about 10nm. The sacrificial silicon dioxide layer 245 is then removed (see FIG.1M) using a conventional isotropic etch (e.g. an aqueous hydrofluoricacid). As a result of the formation and then the removal of thesacrificial silicon dioxide 245, the surface of each of the crystallinesemiconductor materials 230 and 231 is smoother and some of the sidewalldefects are removed. The etch stop layers 211 and 216 prevent the etchexpedient used to remove the thermal silicon dioxide 245 from contactingthe insulating layers 210 and 220 and the layer 235. This step is notnecessarily required in device fabrication, but can be useful forimproving the gate dielectric properties by, for example, reducinginterface traps. The step may be omitted if the silicon defects areknown not to be detrimental for the device being fabricated.

The exposed portion of the crystalline semiconductor material 230defines the physical channel length of the MOSFET device that is beingformed, and the exposed portion of the crystalline semiconductormaterial 231 defines the physical channel length of the JFET device thatis being formed.

Next, a layer of gate dielectric 250 is formed on the exposed portion ofthe crystalline semiconductor materials 230 and 231. Suitable dielectricmaterials includes, for example, thermally-grown silicon dioxide,silicon oxynitride, silicon nitride or metal oxide. The thickness of thegate dielectric 250 is about 1 nm to about 20 nm. One example of asuitable thickness is 6 nm. In one embodiment, the silicon dioxide layeris grown by heating the integrated circuit structure 200 to atemperature in a range of about 700 degrees C. to about 1000 degrees C.in an oxygen-containing atmosphere. Other expedients for forming thegate dielectric 250 may include chemical vapor deposition, jet vapordeposition or atomic layer deposition, all of which are contemplated assuitable. Conditions for forming the gate dielectric 250 of the desiredthickness are well known to those skilled in the art.

Since the gate dielectric 250 is not required for a JFET device, thegate dielectric in the MOSFET region is masked and a wet etch applied tothe structure to remove the gate oxide 250 in the JFET region. FIG. 1Nillustrates the device structure following this step.

Referring to FIG. 10, in the MOSFET region, a gate electrode is formedsurrounding the gate dielectric 250, by depositing a layer 255 ofsufficiently conformal and suitable gate material. For example, a layerof doped amorphous silicon, in which the dopant is introduced in situ,is deposited and then crystallized to form doped polycrystallinesilicon. This step must be accomplished using conditions that do notsignificantly affect the dopant profiles of the dopants in thecrystalline semiconductor material 230. Other examples of suitable gateelectrode materials include silicon-germanium andsilicon-germanium-carbon. Metals and metal-containing compounds thathave a suitably low resistivity and are compatible with the gatedielectric material and the other semiconductor processing steps, arealso contemplated as suitable gate electrode materials. It isadvantageous if the gate material has a work function near the middle ofthe band gap of the semiconductor plug material. Examples of such metalsinclude titanium, titanium nitride, tungsten, tungsten silicide,tantalum, tantalum nitride and molybdenum. Suitable expedients forforming the gate electrode material include chemical vapor deposition,electroplating and combinations thereof.

It is known that the JFET requires a pn junction in the channel (i.e.,the crystalline semiconductor material 231). One method for forming aregion of opposite conductivity type to the channel is discussed below.With reference to FIG. 1P, in the JFET region, a gate electrode isformed surrounding the crystalline semiconductor material 231 bydepositing a layer 256 of sufficiently conformal and suitable JFET gatematerial. For example, a layer of doped amorphous silicon, in which thedopant is introduced in situ, is deposited and then crystallized to formdoped polysilicon crystalline. The dopant type of the layer 256 isopposite to the dopant conductivity of the semiconductor material 231.In the embodiment where the JFET gate and MOSFET gate are formed inseparate steps, the MOSFET gate material deposition step also depositsgate material in the JFET region. It is then necessary to etch theMOSFET gate material from the JFET region and then deposit JFET gatematerial. Finally, the JFET gate material is etched from the MOSFETregion. Therefore, it is preferable to use the same material for boththe layers 255 (the MOSFET gate material) and 256 (the JFET gatematerial). Thus, the layers can be formed simultaneously, eliminatingthe etching steps referred to above. In any case, when doped polysiliconis used for the JFET gate material, during the subsequent dopantdrive-in thermal process, the polysilicon dopants are driven into theJFET channel (the crystalline semiconductor material 231) to form the PNjunction required for the JFET device. The gate material can also bemetal, creating a Szhottky junction and the attendant depletion regionwhen in contact with a semiconductor material.

Referring to FIG. 1Q, the layers 255 and 256 are patterned to form thegate 265 of the MOSFET device and the gate 266 of the JFET device. Thegate configuration is largely a matter of design choice. The gates 265and 266 surround the portion of the crystalline semiconductor material230 and 231 forming the channels of the respective devices.

FIG. 1Q shows the finished MOSFET and JFET device structures. Dopantsare then driven into the crystalline semiconductor material 230 and 231by solid phase diffusion from the insulating layers 210 and 220 to formsource/drain extensions 270 of the MOSFET device and the source/drainextensions 272 of the JFET device. In solid phase diffusion, an oxide(e.g., silicon oxide) serves as the dopant source. At elevatedtemperatures, the dopant is driven from the doped oxide to the adjacentundoped (or lightly doped) regions of the crystalline semiconductormaterials 230 and 231. This technique is advantageous because the dopedarea is defined by the interface between the crystalline semiconductormaterials 230 and 231 and the insulating layers 210 and 220 that serveas the dopant source, and allows the formation of self-alignedsource/drain extensions (i.e. the source drain extensions are alignedwith the gate). Examples of solid phase diffusion techniques aredescribed in Ono, M., et al, “Sub-50 nm Gate Length N-MOSFETS with 10 nmPhosphorus Source and Drain Junctions,” IEDM 93, pp. 119-122 (1993) andSaito, M., et al., “An SPDD D-MOSFET Structure Suitable for 0.1 and Sub0.1 Micron Channel Length and Its Electrical Characteristics,” IEDM 92,pp. 897-900 (1992), which are hereby incorporated by reference.

The concentration of the dopant in source/drain extensions 270 and 272is typically about at least 1×10¹⁹/cm³, with dopant concentrations ofabout 5×10¹⁹/cm³ contemplated as advantageous. With this solid phasediffusion technique, very shallow source and drain extensions areobtainable. The source/drain extensions 270 and 272 are shown aspenetrating into the crystalline semiconductor material 230 and 231,respectively, preferably less than one half the width of the crystallinesemiconductor material 230 and 231. Limiting the dopant penetrations inthis manner avoids significant overlap in the doped regions fromopposite sides of the crystalline semiconductor material 230 and 231.Also, the distance that the source/drain extensions 270 and 272 extendunder the gate is preferably limited to less than one-fourth of the gatelength. In the resulting structure, the net concentration of dopants inthe source/drain extensions 270 and 272 are of the opposite type thanthat present in the now-formed channels 280 and 282 of the MOSFET andJFET respectively.

In yet another embodiment, a thin layer (e.g., a thickness of about 25nm) of undoped silicon dioxide is formed over the source 205. Referringto FIG. 1E, this layer (not shown) acts as a barrier to undesirablesolid phase diffusion from the insulating layer 210, (the dopantsource), down through the source 205 and then up into the crystallinesemiconductor materials 230 and 231.

In accordance with the teachings of the present invention, twoclosely-matched JFETs can be fabricated by sharing the same sacrificiallayer. Since the sacrificial layer defines the gate length, the JFETsare closely matched if the source, drain and channel regions aresimilarly doped and the JFETs utilize the same gate electrode material.Also, the JFET channel is not lithographically controlled, therefore thechannel length is not limited by lithographic process constraints. AJFET constructed according to the teachings of the present invention canbe operated as a conventional JFET and as a voltage-controlled resistor.

An architecture and process have been described that is useful forforming junction field-effect transistors in a circuit structure. Whilespecific applications of the invention have been illustrated, theprincipals disclosed herein provide a basis for practicing the inventionin a variety of ways and a variety of circuit structures, includingstructures formed with Group III-IV compounds and other semiconductormaterials. Although the exemplary embodiments pertain to voltagereplacement gate JFETs, numerous variations are contemplated. Stillother constructions not expressly identified herein do not depart fromthe scope of the invention, which is limited only by the claims thatfollow.

1. A process for fabricating an integrated circuit structure comprising:providing a semiconductor substrate; forming in the semiconductorsubstrate a first device region of a first conductivity type, the firstdevice region selected from the group consisting of a source region anda drain region; forming a multilayer stack comprising at least threematerial layers over the first device region; forming a first and asecond window in the multilayer stack, wherein the first and secondwindows terminate at the first device region; forming a semiconductormaterial within the first and the second windows to form a first and asecond semiconductor plug each having a first end and a second end,wherein the first end of each semiconductor plug is in contact with thefirst device region, and wherein the first and the second semiconductorplugs are of a second conductivity type; forming a second device regionof the first conductivity type at the second end of the firstsemiconductor plug, the second device region selected from the groupconsisting of a source region and a drain region, wherein one of thefirst and the second device regions is a source region and the other isa drain region; forming a third device region of the first conductivitytype at the second end of the second semiconductor plug, the thirddevice region selected from the group consisting of a source region anda drain region, wherein one of the first and the third device regions isa source region and the other is a drain region; removing a materiallayer of the multilayer stack to expose a portion of the first and thesecond semiconductor plugs; forming a dielectric material layer on theexposed portion of the first semiconductor plug; forming a region of thefirst conductivity type on the exposed portion of the secondsemiconductor plug; and forming a gate electrode in contact with thedielectric material layer.
 2. The process of claim 1 wherein thematerial layer of the multilayer stack is removed by etching, wherein afirst layer of the multilayer stack has a first etch rate, the secondmaterial layer has a second etch rate, and a third material layer has athird etch rate, and wherein the second etch rate is at least ten timesfaster than the first etch rate.
 3. The process of claim 2 wherein amaterial of the first material layer and the third material layercomprises an electrically insulating material.
 4. The process of claim 2further comprising the step of forming an etch stop layer over the firstmaterial layer, over the second material layer or over both of the firstand second material layers.
 5. The process of claim 1 further comprisingforming a diffusion barrier layer over the first device region beforeforming the multilayer stack.
 6. A process for fabricating a verticaltransistor comprising: providing a semiconductor substrate; forming inthe semiconductor substrate a first device region of a firstconductivity type, the first device region selected from the groupconsisting of a source region and a drain region; forming a multilayerstack comprising at least three material layers over the first deviceregion; forming a window in the multilayer stack extending to the firstdevice region; forming semiconductor material within the window to forma semiconductor plug in the multilayer stack, wherein the semiconductorplug comprises a first end in contact with the first device region and asecond end, and wherein a material of the semiconductor plug is of asecond conductivity type; forming a second device region of the firstconductivity type at the second end of the semiconductor plug, thesecond device region selected from the group consisting of a sourceregion and a drain region, wherein one of the first and second deviceregions is a source region and the other is a drain region; removing amaterial layer of the multilayer stack to expose a portion of thesemiconductor plug; and forming a region of the first conductivity typeon the exposed portion of the semiconductor plug.
 7. The process ofclaim 6 wherein the multilayer stack comprises a first, a second and athird material layer, and wherein the step of removing the materiallayer comprises etching the second material layer, and wherein the firstlayer has a first etch rate, the second layer has a second etch rate,and the third layer has a third etch rate, and wherein the second etchrate is at least ten times faster than the first etch rate.
 8. Theprocess of claim 7 wherein a material of the first material layer andthe third material layer comprises an electrically insulating material.9. The process of claim 7 further comprising a step of forming an etchstop layer over the first material layer, over the second material layeror over both the first and the second material layers.
 10. The processof claim 6 further comprising forming a diffusion barrier layer over thefirst device region before forming the multilayer stack.
 11. Anintegrated circuit structure comprising first and second verticalfield-effect transistors, wherein the first vertical field-effecttransistor comprises: a semiconductor substrate having a major surfaceformed along a plane; a first doped region of a first conductivity typeformed in the surface; a second doped region of a second conductivitytype overlying the first doped region; a third doped region of the firstconductivity type overlying the second doped region; a dielectricmaterial layer adjacent the second doped region; a first gate adjacentthe dielectric material layer; wherein the second vertical field-effecttransistor comprises: a fourth doped region of the first conductivitytype formed in the surface; a fifth doped region of the secondconductivity type overlying the fourth doped region; a sixth dopedregion of the first conductivity type overlying the fifth doped region;and a second gate of the first conductivity type adjacent the fifthdoped region.
 12. The integrated circuit structure of claim 11 furthercomprising a diffusion barrier layer overlying the first doped region.13. The integrated circuit structure of claim 11 wherein the second andthe third doped regions are formed within a respective first and asecond window formed in material layers overlying the semiconductorsubstrate.
 14. The integrated circuit structure of claim 11 wherein thefirst and the second gates comprise a material selected from the groupconsisting of doped polysilicon crystalline, doped amorphous silicon,doped silicon-germanium, doped silicon-germanium-carbon, metals andmetal compounds.
 15. The integrated circuit structure of claim 14wherein the metals and metal compounds are selected from the groupconsisting of titanium, titanium nitride, tungsten, tungsten suicide,tantalum, tantalum nitride, molybdenum, aluminum and copper.
 16. Theintegrated circuit structure of claim 11 wherein the first and thefourth doped regions comprise a first source/drain region of arespective first and second field effect transistor, the second and thefifth doped regions comprise a channel region of the respective firstand second field effect transistors, and the third and the sixth dopedregion comprise a second source/drain region of the respective first andsecond field effect transistors.
 17. A field-effect transistor structurecomprising: a semiconductor substrate having a major surface along aplane; a first doped region of a first conductivity type disposed in thesurface; a second doped region of a second conductivity type overlyingthe first doped region; a third doped region of the first conductivitytype overlying the second doped region; and a gate region of the firstconductivity type adjacent the second doped region.
 18. A field effecttransistor structure comprising: a semiconductor substrate having amajor surface formed along a plane; a first doped region of a firstconductivity type disposed in the surface; a first insulating layeroverlying the first doped region; a first etch stop layer overlying thefirst insulating layer; a second insulating layer overlying the firstetch stop layer; a second etch stop layer overlying the secondinsulating layer; a third insulating layer overlying the second etchstop layer; a second doped region of a second conductivity type disposedin a window extending downwardly from the third insulating regionthrough the first insulating region; a third doped region of the firstconductivity type overlying the second doped region; a fourth dopedregion of the second conductivity type disposed on an exposed surface ofthe second doped region.